FIG. 1 shows a conventional implementation of a voltage regulator 102 coupled to a CPU 104 to provide it with a regulated voltage supply VR. The CPU requests a desired voltage by way of a voltage identification (VID) command to the VR 102. The voltage that it actually receives (Vin), however, will be less than that generated by the VR due to a voltage drop across the loadline, represented by resistor block R. This resistance includes the output resistance from the voltage regulator, as well as resistances from the connections (pins, contacts, traces, etc.) from the regulator to the CPU.
The loadline resistance determines droop voltages for currents between minimum and maximum CPU loads. It also affects CPU maximum frequency (performance) and maximum efficiency voltage/frequency. Accordingly, to ensure that the CPU can work adequately over expected temperature and process ranges of deviations, from device to device and environment to environment, a VID guardband is typically used to account for the worst-case loadline. Unfortunately, this can result in wasted power and/or lower maximum attainable performance. Thus, improved approaches would be desired.